;/*-----------------------------------------------------------------------------
; * Name:    startup_S32K3xx_util.S
; * Purpose: S32K3xx startup utilities
; * Rev.:    1.0.0
; *----------------------------------------------------------------------------*/
;/*
; * Copyright (C) 2021 Arm Limited or its affiliates. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */

;                #include "S32K3xx_memmap.h"

                PRESERVE8
                THUMB

                AREA    |.text|, CODE, READONLY
DisableSWT0\
                PROC
                EXPORT  DisableSWT0
                ; Disable SWT 0
                ; code not yet tested
                ; LDR      R2,=SWT_BASE+0x018      // SWT Service Key Register (SK)
                ; LDR      R3,=0x0000C520          // 'Clear Soft Lock Key1'
                ; STR      R3,[R2]                 // Write 'Clear Soft Lock Key1' to SWT_SK
                ; LDR      R3,=0x0000D928          // 'Clear Soft Lock Key2'
                ; STR      R3,[R2]                 // Write 'Clear Soft Lock Key2' to SWT_SK
                ; LDR      R2,=SWT_BASE+0x000      // SWT Control Register (CR)
                ; LDR      R3,=0xFF000000          //
                ; STR      R3,[R2]                 // Disable SWT
                BX       LR                        
                ENDP

InitECC         PROC
                EXPORT InitECC
                ; Initialize SRAM
                LDR      R2,=0
                LDR      R3,=0
                LDR      R4,=RAM_START__
                LDR      R5,=RAM_SIZE__
                
                LSRS     R5,R5,#3
SRAM_Loop
                STRD     r2,r3,[R4,#0]
                ADDS     R4,R4,#0x08
                SUBS     R5,R5,#1
                CMP      R5,#0x00
                BNE      SRAM_Loop
        
                ; Initialize DTCM
                LDR      R2,=0
                LDR      R3,=0
                LDR      R4,=DTCM_START__
                LDR      R5,=DTCM_SIZE__
                
                LSRS     R5,R5,#3
DTCM_Loop
                STRD     r2,r3,[R4,#0]
                ADDS     R4,R4,#0x08
                SUBS     R5,R5,#1
                CMP      R5,#0x00
                BNE      DTCM_Loop
        
                ; Initialize ITCM
                LDR      R2,=0
                LDR      R3,=0
                LDR      R4,=ITCM_START__
                LDR      R5,=ITCM_SIZE__
                
                LSRS     R5,R5,#3
ITCM_Loop
                STRD     r2,r3,[R4,#0]
                ADDS     R4,R4,#0x08
                SUBS     R5,R5,#1
                CMP      R5,#0x00
                BNE      ITCM_Loop
        
                BX       LR                     
                ENDP        

; for fast wakeup
FastBoot        PROC
                EXPORT FastBoot 
                LDR      SP, =STACK_START__
				BX	 	 LR
                ENDP
                
;/* default memory mapping used for S32K312 cores
; *  BOOT_HEADER    (r)  :    Start: 0x10000000,   Size: 0x00000100
; *
; *  CM7_0_FLASH   (rx) :     Start: 0x00400000,   Size: 0x00200000
; *  CM7_0_RAM     (rwx):     Start: 0x20400000,   Size: 0x00018000
; *  CM7_0_DTCM    (rwx):     Start: 0x20000000,   Size: 0x00010000
; */
BOOT_HEADER_START  EQU 0x10000000
BOOT_HEADER_SIZE   EQU 0x00000100

; /* CM7 0 */
CM7_0_FLASH_START  EQU 0x00400000
CM7_0_FLASH_SIZE   EQU 0x00200000

CM7_0_RAM_START    EQU 0x20400000
CM7_0_RAM_SIZE     EQU 0x00018000

CM7_0_DTCM_START   EQU 0x20000000
CM7_0_DTCM_SIZE    EQU 0x00010000

CM7_0_ITCM_START   EQU 0x00000000
CM7_0_ITCM_SIZE    EQU 0x00008000

FLASH_START__      EQU    CM7_0_FLASH_START
FLASH_SIZE__       EQU    CM7_0_FLASH_SIZE
RAM_START__        EQU    CM7_0_RAM_START
RAM_SIZE__         EQU    CM7_0_RAM_SIZE
DTCM_START__       EQU    CM7_0_DTCM_START
DTCM_SIZE__        EQU    CM7_0_DTCM_SIZE
ITCM_START__       EQU    CM7_0_ITCM_START
ITCM_SIZE__        EQU    CM7_0_ITCM_SIZE
STACK_START__      EQU    RAM_START__ + RAM_SIZE__

                ALIGN

                END
